20th NASCUG Meeting

June 2, 2014

1:00 - 1:30 Pm Registration
1:30 - 1:40 Pm Welcome, Agenda & Introduction
NASCUG Program Committee
1:40 - 2:30 Pm Keynote: Introducing the Universal Verification Methodology (UVM) in SystemC and SystemC AMS
Karsten Einwich, Fraunhofer IIS
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2:30 - 2:40 Pm Standards Update from Accellera Systems Initiative
Shishpal Rawat, Accellera Systems Initiative Chair
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2:40 - 2:50 Pm SystemC Update from Accellera Systems Initiative
Mike Meredith, SystemC Synthesis Working Group Vice-Chair
2:50 - 3:15 Pm An Approach to Verification of Many-Core Systems Using the Software Virtual Platform
Victoria Mitchell, Altera
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3:15 - 3:30 PM Social & Break
3:30 - 4:20 Pm Out-of-Order Parallel Simulation of SystemC Models using Intel MIC Architecture
Rainer Doemer, University of California Irvine
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4:20 - 4:45 PM S2CBench: Synthesizable SystemC Benchmark Suite for High-Level Synthesis
Anushree Mahapatra, The Hong Kong Polytechnic University
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4:45 - 5:10 PM Reusable Model of AMBA AXI4 Communication Protocol for HLS-based Design Flow
Amaranatha Reddy, CircuitSutra Technologies
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5:10 - 5:25 PM Awards & Closing
5:25 - 6:00 PM Reception & Professional Networking

 

 

Abstracts

Keynote: Introducing the Universal Verification Methodology (UVM) in SystemC and SystemC AMS

This presentation introduces the Universal Verification Methodology (UVM) built in SystemC/C++ (UVM-SystemC), to advance current system-level verification practices. UVM-SystemC enables the creation of structured, modular, configurable and reusable testbench environment. Unlike other initiatives to create UVM in SystemC, the presented proof-of-concept class library uses identical constructs as defined in the UVM standard for test and sequence creation, verification component and testbench configuration and execution by means of simulation. Users familiar with either SystemC and/or UVM will immediately feel comfortable to start using UVM-SystemC right away.

In a nutshell, the talk describes the concepts of UVM-SystemC and shows how they can be applied to real-world designs from the digital and mixed-signal domains:

  • Basic UVM classes and their function are introduced
  • Differences with respect to UVM in SystemVerilog are highlighted
  • (Hierarchical) UVM sequences describing test scenarios are discussed
  • Example: SystemC AMS timed dataflow driver in UVM-SystemC

UVM-SystemC has been developed in the research project VERDI (Verification for heterogeneous Reliable Design and Integration, funded by the European Union's Seventh Framework Programme (FP7), including the partners NXP, Infineon, Continental, Magillem, UPMC, and the Fraunhofer Institute for Integrated Circuits.

The UVM-SystemC Language Reference Manual and associated class library will be handed to the Accellera Systems Initiative enabling further development and standardization.

 

An Approach to Verification of Many-Core Systems Using the Software Virtual Platform

Massive many-core systems face particular challenges for verification of all kinds: architectural, design, as well as software. Coding and debug practices have evolved to deliver non-intrusive visibility into the run-time software at real-time speeds. How can we do the same for DV? We apply an intriguing application of the software virtual platform. We demonstrate a method to verify many-core operations, such as inter-processor communications and resource management, to ensure that what happens within the many-core design accurately maps to the end result, all without adding significant software demands to the DV and test teams.

 

Out-of-Order Parallel Simulation of SystemC Models using Intel MIC Architecture

This talk presents a project of CECS and Intel which builds a parallel SystemC simulation framework that is fully compliant with the SystemC execution semantics. We employ an out-of-order scheduling technique that exploits maximum parallelism without loss of accuracy. The project targets modern many-core platforms, in particular Intel's Many-Integrated-Core (MIC) architecture. Early results on highly parallel applications show simulation speedup by orders of magnitude.

 

S2CBench: Synthesizable SystemC Benchmark Suite for High-Level Synthesis

High-Level Synthesis (HLS) is being increasingly used for commercial VLSI designs. This has led to the proliferation of many HLS tools. In order to evaluate their performance and functionalities, a standard benchmark suite in a common language supported by all of them is required. This paper presents a benchmark suite, which complies with the latest Synthesizable SystemC standard, called "S2CBench: Synthesizable SystemC Benchmark." The benchmarks have been carefully chosen to not only include applications of different sizes and from various domains typically used in HLS (e.g., encryption, image and DSP application), but also to test specific optimization techniques in each of them. This allows an easy comparison of not only Quality of Results (QoR) of the different HLS tools under review, but also to test their completeness.

 

Reusable Model of AMBA AXI4 Communication Protocol for HLS-based Design Flow

As the SoC complexity keeps on increasing and as RTL code size is becoming huge, designing or reusing IPs, verifying them, optimizing them for constraints like area, power, performance while meeting time to market targets is becoming difficult. That leads to serious discussions about moving up one abstraction level above RTL — i.e., to High Level Synthesis (HLS). In this presentation we describe how we used the HLS design flow to design the AXI communication protocol. The AXI model was developed using Synthesizable SystemC Subset, and was synthesized using Cadence Cynthesizer tool to generate the RTL.

 

 

Sponsored by

ARM Cadence Intel
Mentor Graphics Synopsys  

 

NASCUG is managed by

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