16th NASCUG Meeting

6 June 2011

8:30 - 9:00 Am Registration
9:00 - 9:15 Am Welcome, Agenda & NASCUG Introduction
Tor Jeremiassen, Texas Instruments, USA
9:15 - 9:30 Am OSCI Update
Stan Krolikoski, Open SystemC Initiative, USA
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9:30 - 9:55 AM SystemC IP Generation from Graphics and Verification with a UVM SystemVerilog Testbench
Laurent Isenegger, CoFluent Design, USA
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9:55 - 10:20 AM Verification Closure of SystemC Designs with Functional Coverage
Christoph Kuznik University of Paderborn, Germany
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10:20 - 10:30 AM Break
10:30 - 10:55 AM Standard Methodology for Configuration, Control & Inspection of Models
Girish Verma, CircuitSutra Technologies Pvt Ltd, India
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10:55 - 11:20 AM Software Verification, Analysis and Profiling on SystemC TLM-2.0 Virtual Platforms
Larry Lapides, Imperas Software Ltd, England
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11:20 - 11:45 AM TLM-2.0: Miracle Cure or Snake Oil?
David Black, XtremeEDA Corp, USA
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11:45 AM - NOON Meeting Close and Prize Drawing




SystemC IP Generation from Graphics and Verification with a UVM SystemVerilog Testbench

In the ESL ecosystem, early architecture exploration mainly relies on SystemC Transaction-Level Modeling (TLM) whereas SystemVerilog and Open/Universal Verification Methodologies (OVM/UVM) are widely adopted by verification teams. In this presentation, we describe a methodology that enables taking the best of both worlds, SystemC and SystemVerilog, by using OVM testbenches to verify SystemC IPs generated from graphical functional models. The SystemC models are automatically generated from a graphical description. The advanced verification features of OVM, such as random constrained stimuli generation, are used to stimulate thoroughly the SystemC IP through custom IP Application Programming Interfaces (API) using Direct Programming Interfaces (DPI). Next in the design flow, a RTL version of the IP can be obtained either by manual design or specific SystemC code can be generated from the initial graphical model for High-Level Synthesis (HLS). At this point, the OVM testbench developed for the SystemC TLM IP verification can be partially reused for RTL verification, reducing significantly the RTL testbench development time. The generated TLM IP may also serve as a golden reference model and be executed within the verification testbench in parallel with the RTL version."

Verification Closure of SystemC Designs with Functional Coverage

In the area of dynamic verification of virtual prototypes, functional coverage is a valuable tool for answering the "Are we done?" question and achieving verification closure. Recent verification methodologies such as OVM and UVM contain multi-language support that provides a basic SystemC version. However, due to language shortcoming they cannot be utilized for the same amount of verification tasks in the SystemC ecosystem as in other supported hardware design and verification languages. In this presentation, we propose to boost the verification capabilities of SystemC by implementing functional coverage collection and evaluation according to the same metric as defined in the widely accepted IEEE-1800 SystemVerilog cover group feature. We implement a functional coverage library to enable coverage-driven verification of SystemC designs on multiple levels of abstraction enabling value, transition, and expression coverage. To our knowledge, the overall functionalities are not available in the IEEE-1666 SystemC standard or the SCV add-on library, nor are they complete compared to the aforementioned in any publicly available SystemC library.

Standard Methodology for Configuration, Control & Inspection of Models

In this presentation, we will discuss about the upcoming OSCI CCI standard. For the widespread adoption of SystemC modeling, it is necessary that modeling methodologies should be standardized. The OSCI TLM-2.0 standard has provided the model-to-model interoperability; OSCI CCI will take the standardization effort to next level by providing the model-to-tool interoperability. CCI will define the standard mechanism to instrument the model and standard interface to configure, control and inspect the SystemC model from an ESL tool. In the first release, only the configuration part will be covered. A SystemC model that is instrumented by defining the configuration parameters as per CCI standard can be directly configured, controlled or inspected by any CCI compliant ESL tool. Different type of parameters are required for providing different kind of configurability in the model. The parameters that define the structure of the model (number of ports, etc.) should not be allowed to be changed after the end of elaboration, the parameters that make the model compliant with the certain IP specification (e.g.. FIFO size, etc.) should not be allowed to change at all, and there can be certain parameters that can be allowed to change at any time in the simulation (e.g., the abstraction level, LT / AT, trace on/off, etc.). We will also discuss modeling practices for better usage of CCI.

Software Verification, Analysis and Profiling on SystemC TLM-2.0 Virtual Platforms

Embedded software is rapidly getting more complex, due to both increasing lines of code and to the increased concurrency enabled by multicore systems on chips (SoCs). Virtual platforms, for simulation of software, have started to attack software problems caused by this increasing code complexity. Virtual platforms are particularly effective for the development of hardware-dependent software, such as firmware, drivers, operating systems and bare metal applications. However, just as with hardware development, software simulation is a necessary but not sufficient technology. Other tools are needed to help analysis, optimize and verify the software.

In this presentation, technology will be discussed for performing these tasks. While not discussing the details of building the virtual platform, the importance of having fast processor models with native TLM-2.0 interfaces will be brought out. The native interface enables simulation of the processor as just another component within the SystemC environment, as opposed to co-simulation together with, or in parallel with, the SystemC virtual platform. Moving on to the tools, the importance of non-intrusive tools that do not create ambiguities in the results will be discussed. Also, building in knowledge of the CPUs and operating systems to enable additional capabilities is discussed. Finally, a brief discussion of different tools required by software development teams will be presented, together with results for using some of these tools, such as tracing, code coverage, profiling and memory and cache analysis.

TLM-2.0: Miracle Cure or Snake Oil?

TLM-2.0 is bantered around by every EDA vendor and standards group as the great solution to the electronic design world's problems, but is it? This presentation looks closer at what TLM-2.0 represents in simple terms, and what it is not. The author exposes myths, dark secrets, and light at the end of the tunnel.



Thanks to our sponsors

ARM Cadence Forte Design Systems  
Mentor Graphics Synopsys XtremeEDA  


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Open SystemC Initiative (OSCI) Ecole de technologie superieure
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