15th NASCUG Meeting

28 February 2011
One of many events at SystemC Day 2011

8:30 - 9:00 Am Registration
9:00 - 9:10 Am Welcome, Agenda & NASCUG Introduction
David Black, XtremeEDA
9:10 - 9:25 Am OSCI Update
Eric Lish, OSCI Chairman
View presentation
9:25 - 9:55 AM Keynote: "Navigating the SoC Era"
Jim Hogan, Private Investor, Vista Ventures, LLC
View presentation
View details
9:55 - 11:50 Am Low-cost SystemC Acceleration on Multi-core GNU/Linux Platforms
Cicerone Mihalache, Kotys LLC, USA
View presentation
View abstract
TLM Methodology to Enable Architecture Exploration via Co-simulation of SystemC Models with Legacy C/C++ Models
Knute Lingaard (presenter) & Navaneet Kumar (author) FreeScale, USA/India
View presentation
View abstract
The New IEEE 1666 SystemC Standard
John Aynsley, Doulos Ltd., UK
View presentation
View abstract
A Common System Memory Model for SoC Software and Architecture Models using a SystemC/TLM-2.0 Interface
Ali Poursepanj, LSI, NCD System Architecture Group, USA
View presentation
View abstract
11:50 AM - NOON Meeting Close and Prize Drawing

ADDITIONAL SYSTEMC DAY EVENTS

10:00 AM - 2:00 PM Sponsor Exhibits
12:00 PM – 1:00 PM Town Hall Lunch with OSCI and Accellera
Details: http://dvcon.org/events/eventdetails.aspx?id=121-29
1:30 PM – 5:00 PM DVCon Tutorial: "Software-Driven Verification Using TLM-2.0 Virtual Platforms"
Details: http://dvcon.org/events/eventdetails.aspx?id=121-2-T

 

Keynote: "Navigating the SoC Era"

Jim HoganSoCs are becoming ubiquitous in  semiconductor development. Further, these SoCs are no longer processor-centric, and they are differentiated through the integration of design elements such as multi-CPU, multi-core, DSP cores, hardware accelerators, peripherals and software.  

Industry expert and private investor Jim Hogan will discuss the semiconductor industry’s growing adoption of SoC design, and its reliance on diverse sources of hardware and software IP, developed both internally and externally. 

After considering recent survey data on both IP and verification drivers, Hogan will discuss the challenges that design and verification teams face for impacted areas such as design assembly and verification.

Complex tool capabilities are required. Many are still nascent, with a handful of companies building out SoC Realization functionality organically and by inorganic growth through acquisition.  What can design and development teams do today to drive effective SOC Realization?

Jim Hogan, Private Investor

Jim Hogan has worked in the semiconductor design and manufacturing industry for more than 35 years gaining experience as a senior executive in electronic design automation, semiconductor intellectual property, semiconductor equipment, and fabrication companies.

Jim is currently the managing partner of Vista Ventures, LLC. Jim was a general partner at Telos Venture Partners and senior vice president of business development at Artisan Components Inc., now part of ARM Holdings PLC. He held senior engineering, marketing and operational management positions at Cadence Design Systems, Inc., National Semiconductor Corporation and Phillips Semiconductor. At Cadence, he was an Executive Fellow, President of Cadence Japan, Corporate Vice President of Marketing, and Corporate Vice President for Field Operations. At National Semiconductor and Philips, he established device physics laboratories globally. He was also Chief Operating Officer of Smart Machines, Inc., a semiconductor equipment automation company.

Jim holds a B.A degree in mathematics, a B.S. degree in computer science and an M.B.A all from San Jose State University. He serves on the Board of Advisors at San Jose State's School of Engineering, and on several private companies board of directors Altos, AutoESL(acquired by Xilinx February 2011), Scoperta, Tela Innovations and Shocking Technologies. Additionally Jim serves as a strategic advisor to several public technology companies.

 

Abstracts

Definition of a Flow for Behavioral Synthesis for ESL Systems with a Hardware Module using Dynamic Memory Allocation

The increasing complexity of hardware/software (HW/SW) systems being implemented on System on a Chip (SoC) encourages the development of methodologies to describe the system at a higher level of abstraction. Nowadays, some ESL systems have being modeled from the combination of UML, SystemC and C/C++. The present work defines a behavioral synthesis flow that enables a HW/SW system, described in UML-ESL, to have a hardware module that makes use of dynamic memory allocation. In this way, we have developed a tool capable of doing the synthesis of hardware modules that use dynamic memory allocation, functions as malloc and free, where the hardware module is described in SystemC. This tool is called Dynamic Allocation Synthesis (DAS). The DAS tool generates a hardware module called Allocator which is added to the described system. To generate the Allocator, it allows the simulation and the choice of parameters which have the best performance, as memory consumption and quantity of internal fragmentation. The proposed flow achieves the implementation of a hardware module in a Field Programmable Array (FPGA), using high-level synthesis tools such as Cynthesizer from Forte Design Systems.

Low-cost SystemC Acceleration on Multi-core GNU/Linux Platforms

Long simulation times have a big impact on the cost and time-to-market of a System on Chip (SoC) due to the iterative nature of the debugging process. SystemC ESL language is used today in all aspects of SoC design (virtual platform, verification, synthesis). Acceleration of SystemC applications is key for increasing the rate of bug fixing. We present a low-cost technique that speeds up a SystemC application on a GNU/Linux platform in direct correlation with the number of CPU cores if certain conditions are met. Low-complexity TLM-2 inter-process adapters split the simulation on multiple GNU/Linux processes, each process running on one core, with minimal modification of the original code of the SystemC application.

TLM Methodology to Enable Architecture Exploration via Co-simulation of SystemC Models with Legacy C/C++ Models

Early availability of software virtual platform has been a requirement of architects. These virtual platforms are developed by integrating high-fidelity C/C++/SystemC simulation models of individual IP blocks. It's often a challenging task to do a seamless platform integration as these models may not have a common modeling framework.

This paper presents an OSCI TLM-2.0-based methodology to address this model interoperability issue. The methodology has been applied to co-simulate legacy C/C++ models (includes Power cores, Interconnect Fabric, IO devices, DDRC, etc.) together with SystemC-based models (includes DSP cores, DDR target, IO devices, etc.). The legacy C/C++ models, though cycle-accurate, are based on an internal clock-driven simulation framework. They have their own clock management and simulation control mechanism. The paper describes how such legacy models can be made to communicate effectively with SystemC models. The paper also demonstrates how clock determinism and simulation control issues can be resolved between such heterogeneous subsystems during integration.

The work described in this paper has enabled complete re-use of existing C/C++ legacy models and successfully demonstrated quicker platform integration (with SystemC models) without any significant impact on functional and cyclic accuracy of the models.

The New IEEE 1666 SystemC Standard

The IEEE SystemC Standard is currently being revised and updated, with the new standard due to be published later in 2011. This new version of the SystemC standard will for the first time include the TLM-1 and TLM-2.0 libraries. Meanwhile, OSCI is working to ensure that the SystemC Proof-of-Concept simulator tracks any changes to the IEEE standard. This presentation will give a concise technical summary of the most important new and revised features in the SystemC standard, will give a behind-the-scenes insight into the rationale behind the changes, and will show examples to illustrate the new features in action.

A Common System Memory Model for SoC Software and Architecture Models using a SystemC/TLM-2.0 Interface

Systems on a chip (SoCs) generally contain a set of modules (clients) that access a shared memory sub-system (servers) through a memory interconnect (i.e., crossbar). The clients send memory requests to the system memory (servers) while an application is running on the chip.

Architecture models are used to study the performance of the SoCs. Software models are generally used for software development and debugging. Architecture models are time-aware transaction models while software models are register-accurate. Architecture models require accurate memory sub-systems plus representative application workload models. Clients in these models are basically traffic generators that can send traffic to the memory sub-system similar to real applications.

A common memory sub-system implemented in SystemC/TLM-2.0 can be shared by both architecture and software models. In these models, the client traffic generators are initiators and servers are targets. This presentation briefly describes general SoC topologies and how a common memory sub-system implemented in SystemC/TLM-2.0 can be shared by both architecture and software SoC models. These models were implemented and used for architecture analysis and software development at LSI Network Computing Division.

 

 

Thanks to our sponsors

ARM Cadence Forte Design Systems  
Mentor Graphics Synopsys XtremeEDA  

 

NASCUG is managed by

Open SystemC Initiative (OSCI) Ecole de technologie superieure
XtremeEDA Marketing on Demand