11th NASCUG Meeting Agenda & Presentations

27 July 2009

1:00 - 1:30 pm Registration
1:30 - 1:40 pm Welcome, Agenda & NASCUG Introduction
Jean-François Boland, École de technologie supérieure (ETS) University, Canada
1:40 - 1:50 pm OSCI Update
Mike Meredith, President, OSCI
View presentation
1:50 - 2:50 pm A Tool for Assertion-Based Verification of TLM Platforms
Luca Ferro, TIMA Laboratory, Grenoble, France
View presentation
SystemC-AMS for the Design of Complex Analog/Mixed-signal SoCs
Karsten Einwich, Fraunhofer IIS/EAS, Germany
View presentation
Modeling a Virtual MPU
David C Black, XtremeEDA, USA
View presentation
2:50 - 3:05 pm Break
3:05 - 3:20 pm Configuration, Control, & Inspection (CCI) WG Update
Trevor Wieman, Intel
View presentation
3:20 - 4:00 pm Using TLM-2.0 Extensions for Bus Locking and Snooping
John Aynsley, Doulos, UK
View extended presentation
High-speed Packet Router Development in SystemC
William Gnadt, Lockheed Martin MS2, USA
View presentation
4:00 - 4:55 pm SYSTEMC LIVE! An Interactive Town Hall Meeting
Audience participation is encouraged and prizes awarded in this lively discussion.
Find out more
4:55 - 5:00 pm Survey and Prize Drawing
5:00 - 6:00 pm Networking Reception



A Tool for Assertion-Based Verification of TLM Platforms

Luca Ferro, TIMA Laboratory (Grenoble), France

The context of this presentation is the dynamic (i.e., runtime) assertion-based verification (ABV) of TLM SystemC models. In the ABV framework, logic and temporal assertions written in languages such as PSL (Property Specification Language) and SVA are used to capture the design intent. In the last decade, this approach has widely gained acceptance. We present a methodology and a prototype tool named ISIS for checking temporal properties during the SystemC simulation. We especially focus on properties that express constraints on communications (i.e., properties associated with transactional operations); for example: two communication operations with given characteristics must follow each other, data are transferred at the right place, and so on. Those assertions are expressed in the PSL language, including the possibility to use PSL's modeling layer. The ISIS tool performs the automatic construction of the corresponding TLM-oriented monitors, which are linked to the design under verification to check the assertions during simulation. The tool supports timed as well as untimed TLM descriptions and can be used to monitor properties that involve several channels of different types. The properties are specified through a user-friendly GUI.

SystemC-AMS for the design of complex analog/mixed-signal SoCs

Karsten Einwich, Fraunhofer IIS/EAS, Germany

This presentation will show application areas of the current SystemC-AMS prototype developed by Fraunhofer, using real-life examples of automotive and telecommunication applications used in the industry. Different methods for algorithm design, executable specification, architectural exploration, mixed-signal hardware/software-codesign, and IP protected model exchange will be presented. The significant simulation speed-up by using new abstract modeling and simulation approaches for AMS is explained. The seamless integration of TLM and discrete-event models with analog functions is presented, allowing a true multi-domain system-level design and verification method based on SystemC.

Modeling a Virtual MPU

David C Black, XtremeEDA, USA

This talk illustrates a technique used to model software running on an MPU without the use of an ISS. The approach is better than direct execution, because it better separates software from the simulator code and lacks some of the encumbrances of SystemC (the insertion of wait(), for example). The concept can be extended easily to allow for interrupt drivers and time wheel synchronization. The design used TLM-2.0 modeling to create an environment to allow efficient simulation of the hardware. The talk is a fairly technical discussion of an implementation approach used for real customers.

  • Used successfully on a real-world application.
  • Code snippets and implementation concepts provided.
  • Some details (e.g., error handling) are omitted for time.

Using TLM-2.0 Extensions for Bus Locking and Snooping

John Aynsley, Doulos, UK

The OSCI TLM-2.0 standard includes a base protocol that supports many common features of memory-mapped busses, but omits certain features such as the ability to claim exclusive access to resources on the bus (locking) and to inform the processor when another bus master writes to memory (snooping). This omission is a concern to those modeling specific bus protocols. TLM-2.0 was architected such that functionality can be added to the base protocol using a built-in extension mechanism. This begs the question "How easy is it to do?" This presentation shows how we have been able to use the TLM-2.0 extension mechanism to support simple bus locking and snooping schemes. The purpose of this work is twofold: to demonstrate that the TLM-2.0 extension mechanism is both powerful and straightforward to use, and to give a simple tutorial on how to make effective use of some of the TLM-2.0 infrastructure. We found the TLM-2.0 extension mechanism to be entirely adequate for the task, but we were able to benefit from taking a more disciplined approach to memory management than that provided natively in TLM-2.0.

High-speed Packet Router Development in SystemC

William Gnadt, Lockheed Martin MS2, Syracuse, NY

We use SystemC as part of a larger effort to demonstrate the Model-Based System Engineering Method (MSEM). The primary goal of MSEM is to provide unimpeded, undistorted communication between systems, software, and hardware engineers within an engineering team. A secondary goal is to show cost savings, schedule reduction, and risk reduction through model-based design using SystemC. To that end, the techniques applied in MSEM link requirements, hardware architecture, model development, and results. SystemC modeling provides a mechanism to capture hardware functionality into an “executable specification” leading to a design baseline. For this project, MSEM techniques are used for the development of a high-speed packet router using FPGA hardware. The system-level model is designed and captured in SysML, a systems modeling language. System-level requirements are refined into functional modules and flow down to the high-speed packet router. Various hardware architectures are prototyped in SystemC to evaluate alternatives with the lowest parts count. Performance estimates obtained from the SystemC model demonstrate compliance to routing, throughput, and latency requirements. Key conclusions include: accurate prediction of hardware performance using SystemC, application of Rhapsody to support automatic generation of SystemC code and FPGA hardware descriptions, and interfacing a SystemC model with a separate software model for interface verification.


SYSTEMC LIVE! An Interactive Town Hall Meeting

Audience participation and live polling!

Monday July 27, 2009
4:00-5:00 PM
Room Salon 10, San Francisco Marriott

You are invited to a lively discussion for the system-level design community on the state of SystemC and what lies ahead. Providing an interactive format that encourages audience response and questions, this first ever town hall meeting features an open discussion on SystemC, where it's at and where it's going. Design experts from OSCI Working Groups will address user questions on SystemC and its applications, and the technology standards necessary to meet their challenges today and in the future.

Send us Your Questions! The Town Hall features an audience polling system to instantly capture feedback and provide results in real time. We invite you to send questions in advance to the audience and our design experts. To submit questions in advance, e-mail osci_events@lists.systemc.org. To best use the audience polling devices, please phrase questions as either multiple choice or to elicit "yes" and "no" answers. Questions for the experts may also be open ended.

Win a prize for Most Useful Question! The question that receives the most "yes" responses to our poll of "who asked most useful question" during our forum will receive a prize valued at $200 or more. Questions submitted by an attendee before or during the meeting are eligible. You MUST be present to win.

Featured Experts
Moderated by Ed Sperling, Consulting Editor of Chip Design magazine and System-level Design online community, the town hall meeting features the following OSCI Working Groups and design experts:

  • Analog/Mixed-signal: Dr. Christoph Grimm, AMSWG Vice-Chair
  • Configuration, Control & Inspection: Trevor Wieman, CCIWG Chair
  • Language: Mike Meredith, LWG Chair
  • Synthesis: Andres Takach, SWG Chair
  • Transaction-level Modeling: John Aynsley, TLM-2.0 Reference Manual Author

Topics to be addressed may include:

  • Where should SystemC go?
  • What problems do customers want to solve with SystemC?
  • What problems are/not be addressed that should/not be?
  • What tools need to be developed?
  • What is driving/holding progress?


Thanks to our sponsors

ARM Cadence CoWare
Doulos Forte Design Systems Mentor Graphics
Synopsys Virtutech XtremeEDA


NASCUG is managed by

Open SystemC Initiative (OSCI) Ecole de technologie superieure
XtremeEDA Marketing on Demand